1. Full name: Phan Hai Phong                                        2. Sex: Male

3. Date of birth: 23 May 1982                                         4. Place of birth: Thua Thien Hue

5. Admission decision number: 1118/QĐ-CTSV Dated: 24th December 2012 by the Rector of UET.

6. Changes in academic process: No

7. Official thesis title: Power consumption optimization for network-on-chip architectures.

8. Major: Electronics Engineering                                                9. Code: 62 52 02 03

10. Supervisors: Assoc. Prof. Dr. Tran Xuan Tu

11. Summary of the new findings of the thesis:

Proposed a solution based on the dynamic frequency-frequency control (DVFS) and fuzzy logic method to optimize the energy consumption for the 2D-mesh Network-on-Chip architectures. Modeling and implementing the proposed solution in VHDL language. The components of solution are modeled at the Register Transfer Level (RTL). All of components have been simulated and verified at logic level by using ModelSim software.

Proposed a method to allow evaluating the power consumption efficiency of a Network-on-Chip at system level when applying the DVFS techniques. This method was developed by using the ORION model. This is a high-precision estimating power consumption model for Network-on-Chip which is widely used in many simulation software.

12. Practical applicability, if any: This thesis has proposed a model of a voltage-frequency controller which was applied on the router of a network on chip. This model can be synthesized as a hardware solution to apply on a low power network on chip.

13. Further research directions, if any:

Study to improve the prediction ability of fuzzy logic processor (FLP). It can be done by increasing the number of membership functions and rules in the FLP.

Study to apply machine learning (ML) models in the controller. The ML models will be used to predict the traffic load and give the decision to change the voltage and frequency of the system.

14. Thesis-related publications:

Hai-Phong Phan, Xuan-Tu Tran (2015), “Design and Modeling of a Voltage-Frequency Controller for Network-on-Chip Routers base on Fuzzy-Logic”, VNU Journal of Computer Science and Communication Engineering (JCSCE), pp. 56-65, Vol. 31, No. 2, 2015, ISSN: 0866-8612.

Hai-Phong Phan, Xuan-Tu Tran, Tomohiro Yoneda (2017), “Power Consumption Estimation using VNOC2.0 Simulator for a Fuzzy-Logic based Low Power Network-on-Chip”, In Procceedings of the 2017 IEEE International Conference on Integrated Circuit Design and Technology (IEEE ICICDT), Texas, USA.

Hai-Phong Phan, Xuan-Tu Tran (2016), “Fuzzy-Logic based Low Power Solution for Network-on-Chip Architectures”. In Proceedings of the 2016 International Conference on Advanced Technologies for Communications (IEEE ATC), 12-14 October 2016, Hanoi, Vietnam.

Hai-Phong Phan, Xuan-Tu Tran (2015), “A Fuzzy-Logic based Voltage-Frequency Controller for Network-on-Chip Routers”, In Proceedings of the 11th Conference on PhD Research in Microelectronics and Electronics (IEEE PRIME 2015), Glasgow, Scotland, 29 June - 2 July, 2015.

Hai-Phong Phan, Xuan-Tu Tran (2014), “Thiết kế và mô hình hoá bộ xử lý lô-gic mờ trong điều khiển tần số - điện áp”. In Proceedings of the 2014 National Conference on Electronics, Communications and Information Technology (REV-ECIT2014), Nha Trang, 18-19/9/2014.